The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a process of forming an interconnection layer buried in a contact hole in an interlayer insulating film.
A connection between a conductive region as of an impurity-diffused layer in a semiconductor substrate or a lower-level wiring layer, and an upper-level wiring layer through the contact hole formed in the interlayer insulating film is one of important techniques in a semiconductor device. In a semiconductor device of a low integration density, contact holes can be of a low aspect ratio, that is, a larger area comparing with the depth. Therefore, the contact holes can be filled by metal such as aluminum when the metal is deposited on the interlayer insulating layer to form the upper-level wiring layer. On the other hand, contact holes of a high integration density device such as a memory device become inevitably a high aspect ratio, that is, a smaller area comparing with the depth. Therefore, so-called buried contact technique in which polycrystalline silicon (hereinafter referred to "polysilicon") is buried as an interconnection material in the contact hole by a process different from the process for forming the upper wiring layer is necessary.
The polysilicon of the interconnection layer is doped with impurity to be low electrical resistant, and fills the contact hole by deposition through a chemical vapor phase deposition (CVD) technique. Three processes for forming interconnection layer are considered: The first comprising forming a doped polysilicon film by CVD while doping impurity and then etching it; the second comprising depositing nondoped polysilicon film and subsequent doping by thermal diffusion or ion implantation; and the third comprising sequentially depositing a nondoped polysilicon film, etching it and doping. The third process is reported in "NIKKEI MICRODEVICES" March, 1989, pp. 70-74, telling that a contact hole is formed, run over with a polysilicon film by CVD and planarized by etch-back, leaving the polysilicon film only in the contact hole. Subsequently ion implantation of impurity and thermal treatment by means of lamp heating are carried out.
The first process can not be used for a contact hole having a aspect ratio of about 1 or more because the deposition of doped polysilicon by CVD can not provide good coverage.
By the second process, it is difficult without subjecting to too thermal treatment to obtain uniform distribution of impurity in the thick polysilicon film formed for filling the contact hole. Ununiform distribution of impurity generally makes the rate of the etching inconstant, resulting in variation in amount and quality of the polysilicon film leaving in the contact hole, and in turn in difficult formation of good connection to the polysilicon film as the interconnection layer.
In the third process, thermal treatment required for the activation must perform without allowing the PN junction already formed in the semiconductor substrate to shift. It, however, is not easy to realize it in the art of highly miniaturized semiconductor elements.
The above-mentioned problem can be solved by the following:
A thin polysilicon film is deposited and an impurity is diffused into it. Next, onto this doped polysilicon film, a thick polysilicon film is deposited to run over a contact hole, and these polysilicon films are etched back, leaving them in the contact hole, thus an interconnection layer being obtainable. A technique of this type is reported in The Digest of Technical Papers, "1987 SYMPOSIUM ON VLSI TECHNOLOGY" pp. 103-104. Generally, the etching back of the polysilicon films mentioned above is conducted by a plasma etching method with a gas producing a large amount of radicals involving fluorine as of sulfur hexafluoride. The plasma of the plasma etching method is produced by applying high frequency power, for example, to external electrodes outside a chamber in which a semiconductor wafer to be etched (worked) is installed and the plasma is produced. Cr else, the plasma is produced in a plasma generating room and introduced into the chamber. The plasma etching uses a chemical reaction of the radicals by the plasma and the material (polysilicon) to be etched, and a sputtering phenomenon by ions can be neglected. Therefore, the plasma etching is called as a chemical dry etching, and generally is isotropic etching.
The application of the plasma etching technique like this to the last-mentioned method, particularly for the etching of the polysilicon film, results in producing unwanted irregularities on the surface of the interconnection layer because doped polysilicon films are etched more rapidly than nondoped polysilicon film. By the plasma etching technique, for example, a polysilicon film doped with phosphorus to a level of about 5.times.10 cm.sup.-3 can be etched at a rate of 1.2 times more than nondoped polysilicon film. Therefore compared with the portion of nondoped polysilicon film projecting from the contact hole the doped polysilicon film surrounding the nondoped-polysilicon portion is etched rapidly to the same level as the surface of the interlayer insulating film. When etching of the nondoped polysilicon film has reached the surface level of the interlayer insulating film, a step results which amounts to an about 20 to 100% to the deposited thickness of the doped polysilicon film. The incorrespondence between the step and the difference in etching rate is due to the microloading effect. Which is apt to occur when the silicon films are etched by the plasma etching method mentioned above. That is, when a polysilicon has a shape finer than a certain size, compared with the center portion, the edge portion is etched rapidly. By the etching speed difference and the microloading effect by the plasma etching method, a narrow groove is produced in the contact hole, and the upper surface of the polysilicon as the interconnection layer in the contact hole becomes irregular. Consequently, the connection between the upper wiring layer and the interconnection layer of polysilicon may be put into poor or high electrical resistance contact.